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rev. 2.2 5/15 copyright ? 2015 by silicon laboratories sl23ep05 sl23ep05 l ow j itter and s kew 10 to 220 mh z z ero d elay b uffer (zdb) features applications benefits description the sl23ep05 is a low skew, low jitter, and low power zero delay buffer (zdb) designed to produce up to five clock outputs from one reference input clock for high speed clock distribution applications. the product has an on- chip pll which locks to the input clock at clkin and receives its feedback internally from the clkout pin. the sl23ep05 is available with two drive strength versions called ?1 and ?1h. the ?1 is the standard-drive version and ?1h is the high-drive version. the sl23ep05 high-drive version operates up to 220 mhz and 180 mhz at 3.3 v and 2.5 v power supplies, respectively. the standard drive version ?1 operates up to 200 mhz and 167 mhz at 3.3 v and 2.5 v, respectively. the sl23ep05 enter into power down (pd) mode if the input at clkin is less then 2.0 mhz or there is no rising edge. in this state all five outputs are tri-stated and the pll is turned off leading to less than 10 a of power supply current draw. ? 10 to 220 mhz operating frequency range ? low output clock jitter: ?? 50 ps-typ cycle-to-cycle jitter ?? 20 ps-typ period jitter ? low output-to-output skew: 30 ps-typ ? low product-to-product skew: 60 ps-typ ? wide 2.5 v to 3.3 v power supply range ? low power dissipation: ?? 16 ma-max at 66 mhz and vdd = 3.3 v ?? 14 ma-max at 66 mhz and vdd = 2.5 v ? one input drives five outputs organized as 4+1 ? spreadthru? pll that allows use of sscg ? standard and high-drive options ? available in 8 pin soic and tssop packages ? available in commercial and industrial grades ? printers and mfps ? digital copiers ? pcs and work stations ? routers, switchers and servers ? digital embedded systems ? up to five distribution of input clock ? standard and high-drive levels to control impedance level, frequency range and emi ? low power dissipation, jitter and skew ? low cost patents pending ordering information: see page 14. pin assignments sl23ep05
sl23ep05 2 rev. 2.2 functional block diagram
sl23ep05 rev. 2.2 3 t able of c ontents section page 1. electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3. input and output frequency range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 4. spreadthru? feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 5. high and low-drive product options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 6. skew and zero delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 7. power supply range (vdd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 8. external components and design considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 8.1. comments and recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 8.2. switching waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 9. pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 10. package outline and dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 10.1. 8-lead soic (150 mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 11. ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
sl23ep05 4 rev. 2.2 1. electrical specifications table 1. dc electrical specifications (v dd = 3.3 v) unless otherwise stated for both c and i grades. parameter symbol test condition min max unit supply voltage vdd 3.0 3.6 v input low voltage vil ? 0.8 v input high voltage vih 2.0 v dd +0.3 v input leakage current iil 0 < vin < 0.8 v ? 10 a input high current iih vin = v dd ? 100 a output low voltage vol iol = 8 ma (standard drive) ? 0.4 v iol = 12 ma (high drive) ? 0.4 v output high voltage voh ioh = ?8 ma (standard drive) 2.4 ? v ioh = ?12 ma (high drive) 2.4 ? v power down supply current iddpd clkin = 0 mhz (commercial) ? 10 a clkin = 0 mhz (industrial) ? 25 a power supply current idd all outputs cl = 0, 66-mhz clkin ? 16 ma table 2. dc electrical specifications (v dd = 2.5 v) unless otherwise stated for both c and i grades. parameter symbol test condition min max unit supply voltage vdd 2.3 2.7 v input low voltage vil ? 0.7 v input high voltage vih 1.7 v dd + 0.3 v input leakage current iil 0 sl23ep05 rev. 2.2 5 table 3. ac electrical specifications (v dd = 3.3 v and 2.5 v) parameter symbol test condition min typ max unit maximum frequency (input=output) 1 fmax 3.3 v high drive 10 ? 220 mhz 3.3 v standard drive 10 ? 200 mhz 2.5 v high drive 10 ? 180 mhz 2.5 v standard drive 10 ? 167 mhz input duty cycle indc <135 mhz, v dd = 3.3 v 25 ? 75 % <135 mhz, v dd = 2.5 v 40 ? 60 % output duty cycle 2 outdc <135 mhz, v dd = 3.3 v 45 ? 55 % <135 mhz, v dd = 2.5 v 40 ? 60 % rise, fall time (3.3v) measured at: 0.8 to 2.0 v 2 tr/f3.3 high drive, cl = 15 pf, >135 mhz ? ? 0.5 ns std drive, cl = 15 pf, <170 mhz ? ? 1.5 ns high drive, cl = 30 pf, <100 mhz ? ? 1.5 ns std drive, cl = 30 pf, <100 mhz ? ? 2.5 ns rise, fall time (2.5) 2 measured at: 0.6 to 1.8 v tr/f2.5 high drive, cl = 15 pf, >135 mhz ? ? 1.5 ns std drive, cl = 15 pf, <135 mhz ? ? 2.5 ns high drive, cl = 30 pf, <100 mhz ? ? 2.5 ns output-to-output skew 2 t 1 all outputs cl = 0, 3.3 v supply, 2.5 v power supply, standard drive ? 30 90 ps all outputs cl = 0, 2.5 v power supply, high drive ? 40 100 ps delay time, clkin rising edge to clkout rising edge 2 t2 pll enabled @ 3.3 v ?100 ? 100 ps pll enabled @2.5 v ?200 ? 200 ps part-to-part skew 2 t3 measured at v dd /2. any output to any output, 3.3 v supply ?150 ? 150 ps measured at v dd /2. any output to any output, 2.5 v supply ?300 ? 300 ps notes: 1. for the given maximum loading conditions. see cl in operating conditions table. 2. parameter is guaranteed by design and characterization. not 100% tested in production.
sl23ep05 6 rev. 2.2 table 4. ac electrical specifications (v dd = 3.3 v and 2.5 v) parameter symbol test condition min typ max unit pll lock time[9] tpllock from 90% of v dd to valid clocks presented on all output clock pins ? ? 1.0 ms cycle-to-cycle jitter ccj * 3.3 v supply, >66 mhz, <15 pf, standard drive ? 50 125 ps 3.3 v supply, >66 mhz, <30 pf, high drive ? 70 140 ps 3.3 v supply, >66 mhz, <30 pf, standard drive ? 80 170 ps 2.5 v supply, >66 mhz, <15 pf, high drive ? 50 80 ps 2.5 v supply, >66 mhz, <15 pf, standard drive ? 90 200 ps 2.5 v supply, >66 mhz, <30 pf, high drive ? 100 250 ps peak period jitter ppj * 3.3 v supply, >100 mhz, <15 pf, standard drive ?3065ps 3.3 v supply, 66?100 mhz, <15 pf, standard drive ?4075ps 3.3 v supply, >66 mhz, <30 pf, high drive ? 60 120 ps 3.3 v supply, >66 mhz, <30 pf, standard drive ? 70 150 ps 2.5 v supply, > 100 mhz, <15 pf, high drive ? 20 45 ps 2.5 v supply, 66?100 mhz, <15 pf, high drive ? 20 60 ps 2.5 v supply, >66 mhz, <15 pf, standard drive ? 60 120 ps *note: typical jitter is measured at 3.3 v or 2.5 v, 30oc with all outputs driven into the maximum specified load.
sl23ep05 rev. 2.2 7 table 5. operating conditions unless otherwise stated v dd = 2.5 v to 3.3 v and for both c and i grades. parameter symbol test condition min max unit 3.3 v supply voltage vdd3.3 3.0 3.6 v 2.5 v supply voltage vdd2.5 2.3 2.7 v operating temperature (ambient) ta commercial 0 70 c industrial ?40 85 c load capacitance cload <220 mhz, 3.3 v with high drive ? 15 pf <200 mhz, 3.3 v with standard drive ? 15 pf <180 mhz, 2.5 v with high drive ? 15 pf <167 mhz, 2.5 v with standard drive ? 15 pf <200 mhz, 3.3 v with high drive ? 22 pf <180 mhz, 3.3 v with standard drive ? 22 pf <167 mhz, 2.5 v with high drive ? 22 pf <134 mhz, 2.5 v with standard drive ? 22 pf <133 mhz, 3.3 v with high drive ? 30 pf <100 mhz, 3.3 v with standard drive ? 30 pf <80 mhz, 2.5 v with high drive ? 30 pf < 67 mhz, 2.5 v with standard drive ? 30 pf input capacitance cin clkin pin ? 5 pf closed-loop bandwidth clbw 3.3 v, (typical) 1-1.5 mhz 2.5 v, (typical) 0.8 mhz output impedance zout 3.3 v, (typical), high drive 29 3.3 v, (typical), standard drive 41 2.5 v, (typical), high drive 37 2.5 v, (typical), standard drive 41
sl23ep05 8 rev. 2.2 table 6. thermal characteristics parameter symbol test condition min typ max unit thermal resistance junction to ambient still air ? 110 ? c/w 1 m/s air flow ? 100 ? c/w 3 m/s air flow ? 80 ? c/w thermal resistance junction to case independent of air flow ? 35 ? c/w table 7. absolute maximum rating parameter test condition min max unit supply voltage, v dd ?0.5 4.6 v all inputs and outputs ?0.5 v dd +0.5 v ambient operating temperature in operation, c-grade 0 70 c ambient operating temperature in operation, i-grade ?40 85 c storage temperature no power is applied ?65 150 c junction temperature in operation, power is applied ? 125 c soldering temperature ? 260 c esd rating (human body model) jedecc22-a114d ?4000 4000 v esd rating (charge device model) jedecc22-c101c ?1500 1500 v esd rating (machine model) jedecc22-a115d ?200 200 v
sl23ep05 rev. 2.2 9 2. general description the sl23ep05 is a low skew, low jitter zero delay buffer with very low operating current. the product includes an on-chip high performance pll that locks into the input reference clock and produces five output clock drivers tracking the input reference clock for systems requiring clock distribution. 3. input and output frequency range the input and output frequency range is the same. however, it depends on v dd and drive levels as given in the below table 8. if the input clock frequency is dc (0 to v dd ), this is detected by an input frequency detection circuitry and all five clock outputs are forced to hi-z. the pll is shutdown to save power. in this shutdown state, the product draws less than 10 a supply current. 4. spreadthru? feature if a spread spectrum clock (ssc) were to be used as an input clock, the sl23ep05 is designed to pass the modulated spread spectrum clock (ssc) signal from its reference input to the output clocks. the same spread characteristics at the input are passed through the pll and drivers without any degradation in spread percent (%), spread profile and modulation frequency. 5. high and low-drive product options the sl23ep05 is offered with high-drive ??1h? and standard-drive ??1? options. these drive options enable the users to control load levels, frequency range and emi control. refer to the ac electrical tables for the details. 6. skew and zero delay all outputs should drive the similar load to achieve output-to-output skew and input-to-output specifications given in the ac electrical tables. however, zero delay between input and outputs can be adjusted by changing the loading of clkout relative to the banks a and b clocks since clkout is the feedback to the pll. 7. power supply range (v dd ) the sl23ep05 is designed to operate in a wide power supply range from 2.250 v (min) to 3.360 v (max). this power supply range complies with 3.3 v+/?10% and 2.5 v+/?10% standard power supply requirements used in most systems. an internal on-chip voltage regulator is used to supply pll constant power supply of 1.8 v, leading to a consistent and stable pll electrical performance in terms of skew, and jitter and power dissipation. table 8. input/output frequency range v dd (v) drive min (mhz) max (mhz) 3.3 high 10 220 3.3 std 10 200 2.5 high 10 180 2.5 std 10 167
sl23ep05 10 rev. 2.2 8. external components and design considerations figure 1. typical application schematic 8.1. comments and recommendations decoupling capacitor : a minimum decoupling capacitor of 0.1 f must be used between vdd and vss on the pins 6 and 4. additional capacitors may be necessary depending on the application. place the capacitor on the component side of the pcb as close to the vdd pin as possible. the pcb trace to the vdd pin and to the gnd via should be kept as short as possible. do not use vias between the decoupling capacitor and the vdd pin. series termination resistor : a series termination resistor is recommended if the distance between the output (ssclk) and the load is over 1.5 inches. the nominal impedance of the ssclk output is about 30 . use 20 resistor in series with the output to terminate 50 trace impedance and place 20 resistor as close to the clock outputs as possible. zero delay and skew control : all outputs and clkin pins should be loaded with the same load to achieve ?zero delay? between the clkin and the outputs. the clkout pin is connected to clkin internally on-chip for internal feedback to pll, and sees an additional 2 pf load with respect to the clock pins. for applications requiring zero input/output delay, the load at the all output pins including the clkout pin must be the same. if any delay adjustment is required, the capacitance at the clkout pin could be increased or decreased to increase or decrease the delay between clocks and clkin. for minimum pin-to-pin skew, the external load at the clocks must be the same.
sl23ep05 rev. 2.2 11 8.2. switching waveforms figure 2. output to output skew figure 3. input to output skew figure 4. part-to-part skew
sl23ep05 12 rev. 2.2 9. pin descriptions figure 5. 8-pin soic table 9. pin descriptions pin number pin name pin type pin description 1 clkin input reference frequency clock input. weak pull-down (150 k ). 2 clk2 output buffered clock output weak pull-down (150 k ). 3 clk1 output buffered clock output. weak pull-down (150 k ). 4 gnd power power ground. 5 clk3 output buffered clock output. weak pull-down (150 k ). 6 vdd power 3.3 v or 2.5 v power supply. 7 clk4 output buffered clock output. weak pull-down (150 k ). 8 clkout output buffered clock output. used for internal feedback to pll input. weak pull-down (150 k ).
sl23ep05 rev. 2.2 13 10. package outline and dimensions 10.1. 8-lead soic (150 mm) figure 6. 8-lead soic (150 mm)
sl23ep05 14 rev. 2.2 11. ordering guide table 10. ordering guide ordering number shipping package package temperature sl23ep05sc-1 tube 8-pin soic 0 to 70c sl23ep05sc-1t tape and reel 8-pin soic 0 to 70c sl23ep05si-1 tube 8-pin soic ?40 to 85c sl23ep05si-1t tape & reel 8-pin soic ?40 to 85c sl23ep05sc-1h tube 8-pin soic 0 to 70c sl23ep05sc-1ht tape & reel 8-pin soic 0 to 70c sl23ep05si-1h tube 8-pin soic ?40 to 85c sl23ep05si-1ht tape & reel 8-pin soic ?40 to 85c SL23EP05BSI-1H tube 8-pin soic ?40 to 85c SL23EP05BSI-1Ht tape & reel 8-pin soic ?40 to 85c notes: 1. the sl23ep05 products are rohs compliant. 2. minimum order quantity (moq) is for production orders. silicon labs provides lesser quantities for pre-production samples.
sl23ep05 rev. 2.2 15 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 email: fminfo@silabs.com internet: www.silabs.com patent notice silicon labs invests in research and development to help our customers differentiate in the market with innovative low-power, s mall size, analog- intensive mixed-signal solutions. silicon labs' extensive patent portfolio is a testament to our unique approach and world-clas s engineering team. silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. additionally, silicon laboratories assumes no responsibility for the functioning of undescribed fea- tures or parameters. silicon laboratories reserves the right to make changes without further notice. silicon laboratories makes no warran- ty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laborato ries assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, in cluding without limitation consequential or incidental damages. silicon laboratories products are not designed, intended, or authorized for use in applica tions intend- ed to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a situation where personal injury or death may occur. should buyer purchase or use silicon laboratories products for any such unintended or unaut horized application, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.

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